1. Field of the Invention
The present invention relates to a method of manufacturing an alignment mark, and, in particular, to a method of manufacturing an alignment mark for aligning an upper layer pattern and a lower layer pattern with each other during the manufacture of an integrated circuit pattern.
2. Description of the Related Art
A semiconductor integrated circuit device (which is referred to as an xe2x80x9cLSIxe2x80x9d hereinafter) is manufactured by a method comprising: a coating (film-forming) step, in which a material film made of a desired material is formed on an LSI substrate (which is referred to as a xe2x80x9cwaferxe2x80x9d hereinafter) to form an LSI element; a photolithographic step, in which a resist pattern is formed by transferring an integrated circuit pattern (which is referred to as a xe2x80x9ccircuit patternxe2x80x9d hereinafter) onto a photosensitive high polymer film (which is referred to as a xe2x80x9cresist filmxe2x80x9d hereinafter); and an etching step, in which the material film disposed beneath a resist film is etched by using the resist pattern as a blocking layer.
An LSI is manufactured stereoscopically by repeating the coating step, the photolithographic step, and the etching step in combination with one another a necessary number of times to thereby form stacked pattern forming layers.
Generally, an original plate (which is referred to as a xe2x80x9cmaskxe2x80x9d hereinafter) is used in the photolithographic step. The original plate comprises a circuit pattern film, made of a material such as chromium that shields light to which the materials exposed, disposed on a material such as a glass substrate through which exposure light is transmitted. The pattern of the circuit pattern film formed on the mask (which is referred to as a xe2x80x9cmask patternxe2x80x9d hereinafter) is imaged on the resist film by magnifying or reducing the pattern using a reflection or projection optical system, whereby the resist is exposed, the resist film is sensitized in a mask pattern, and a resist pattern is formed. Then, on the basis of the resist pattern, the layer formed beneath the resist film is patterned.
When an LSI is manufactured, a stereoscopical LSI element is formed by stacking circuit patterns. LSI performance is influenced to a great extent by the relative accuracy to which the circuit pattern on the wafer that has already been processed and formed, and the circuit pattern that is to be formed by exposure are aligned in the photolithographic step. Therefore, it is essential to align the two circuit patterns so that their positions match with high precision.
In the photolithographic step, the mask and the wafer are aligned relative to each other in order to relatively align with high precision the circuit pattern that has already been processed and formed on the wafer and the circuit pattern that is to be formed by exposure and development.
This alignment is carried out by using marks for detecting an alignment position (alignment marks) formed at the mask and the wafer. The alignment mark at the mask is formed as a portion of the mask pattern. Generally, an exposure device comprises: position measurement means for detecting these two alignment marks and measuring relative alignment thereof; and moving means for moving each of the mask and the wafer to a desired position. Prior to exposure, on the basis of the results obtained from the position measurement means that has detected the two alignment marks and measured relative alignment thereof, the moving means moves at least one of the mask and the wafer, whereby, the alignment mark formed on the wafer and the alignment mark formed on the mask are precisely aligned.
In this case, relative misalignment between the pattern formed during the previous photolithographic step and the pattern underlying this pattern is fed back as alignment correction information during exposure. Accordingly, it becomes possible to align the mask and the wafer with greater precision.
This alignment correction information is obtained by measuring two types of marks: a resist mark formed as a portion of the resist pattern; and a reference mark formed as a portion of a pattern that has been formed beneath the resist pattern.
As an example, description will be given of an alignment mark that is utilized in the photolithographic step in a method of manufacturing a wiring layer. The wiring layer is a main constituent element of the LSI. This method comprises a series of steps in which an interlayer insulating layer is formed on a first wiring layer, a connection hole (which is referred to as a xe2x80x9cvia holexe2x80x9d hereinafter) for electrically connecting the first wiring layer and a second wiring layer that is disposed on the interlayer insulating layer is formed in the interlayer insulating layer, and then, the second wiring layer is formed on the interlayer insulating layer.
In particular, since it is necessary in this method to align with high precision the second wiring layer with the via hole formed in the interlayer insulating layer, it is preferable to form an alignment mark on the interlayer insulating layer when the interlayer insulating layer is formed beneath the second wiring layer.
Various shapes can be used for the alignment mark. Description of a case in which an alignment mark of a pattern (shape) shown in FIG. 8 is used will be given as an example. The alignment mark shown in FIG. 8 is configured such that grooves are disposed, with portions of an upper surface of a wiring pattern disposed beneath the alignment mark being visible in the grooves.
First, when the via hole is formed in the interlayer insulating layer that has been formed uniformly on the first wiring layer, an alignment mark is formed at the same time that the via hole is formed. The alignment mark is formed in a region other than a device region in which a pattern for structuring an LSI, such as a via hole, wiring or circuitry is formed.
Next, a film comprising a conductive material and forming an overlying wiring pattern, and a resist film that has, for example, a thickness of about 300 nm to about 2000 nm are formed uniformly over the entire interlayer insulating layer having the alignment mark formed thereon.
Then, the alignment mark formed on the mask and the alignment mark formed on the interlayer insulating layer are detected by using the mask having the wiring pattern formed thereon. Misalignment between the mask and the wafer is measured, and the result of the measurement is outputted to the moving means. The mask and the wafer are moved relative to each other by the moving means to eliminate any misalignment between the mask and the wafer, whereby the two alignment marks are aligned with high precision. It should be noted that the alignment mark formed on the interlayer insulating layer is detected by detecting a gap between the top surface of the interlayer insulating layer and the bottom of the grooves forming the alignment mark.
However, because the alignment mark is formed on the same layer on which the device pattern, such as a via hole, wiring or circuitry, for forming the LSI is formed, a problem arises in that by-products may be formed on the alignment during device patterning (FIG. 9), whereby the shape of the alignment mark is changed and reliability of the alignment mark is lowered.
Description will be given of an example in which a conductive material is filled in the via hole through which the upper wiring pattern and the lower wiring pattern are electrically connected to each other. First, as shown in FIG. 10A, a first wiring 54 and a second interlayer insulating layer 56 are sequentially formed on a first interlayer insulating layer 52, comprising SiO2 or the like, and a wafer 50. Then, resist is coated on the surface to thereby form a resist film 58.
Next, as shown in FIG. 10B, a via hole 60 is formed in an LSI element forming region of the second interlayer insulating layer 56 by photolithography and etching, and a groove-shaped alignment mark 62 is formed in an alignment mark forming region of the second interlayer insulating layer 56. The alignment mark forming region is a predetermined region outside of the device pattern forming region.
After removing the resist film 58, as shown in FIG. 10C, an electrically conductive film 57 comprising an electrically conductive filling material (e.g., comprising either tungsten or polysilicon or comprising a metal disposed on tungsten, a metal disposed on polysilicon, or a metal disposed on tungsten and polysilicon) is coated uniformly on the entire surface, whereby the entire via hole 60 is filled in with the material. Typically, the via hole 60 is about 0.5 xcexcm or less, and the width W of the alignment mark 62 is about 1 xcexcm to about several xcexcm. Since the alignment mark 62 is larger than the via hole 60, the alignment mark 62 region is not entirely filled in with the filling material.
After the filling material has been coated, it is removed by etch-backing so that only the filling material inside the via hole 60 remains, whereby a plug 59 is formed. Depending on the combination of wiring material and etching gas, when aluminum is contained in the wiring material and chloride is contained in the etching gas, a by-product 70 may be produced at the bottom of the alignment mark 62 due to reaction between a component contained in the exposed wiring material at the bottom of the alignment mark 62 and a component contained in the etching gas, or due to reaction between a component contained in the wiring material, a component contained in the etching gas, and a component in the environmental atmosphere in which a wafer is placed. Because the by-product 70 comprises gel whose volume has expanded, the shape, size, and distribution density of the by-product 70 are non-uniform, it is difficult to remove the by-product 70 by uniform treatment.
Since the by-product 70 is actualized as foreign matter and changes the shape of the alignment mark, as shown in FIG. 9, there is a drawback in that reliability of the alignment mark as a mark for detecting an alignment position is compromised.
An object of the present invention is to provide a method of manufacturing a highly reliable alignment mark, in which by-products are prevented from being formed at an alignment mark position during patterning.
A first aspect of the present invention is a method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together on a wafer, comprising: forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer, forming a second alignment mark by cutting the second pattern layer at a predetermined position thereof on the basis of the first alignment mark, providing a protective layer for protecting the second alignment mark, and forming a predetermined pattern in a pattern forming region of the second pattern layer by using the first alignment mark.
In the method of manufacturing the alignment mark according to the first aspect of the present invention, since a layer for protecting the second alignment mark is provided, even if the first pattern layer is exposed at the bottom of the second alignment mark, the second alignment mark is covered with the protective layer when a pattern is formed on the second pattern layer. Accordingly, drawbacks due to the first pattern layer being exposed and by-products being formed can be eliminated.
For example, if the first pattern layer is a wiring layer comprising an electrically conductive material, and the second pattern layer is an insulating layer serving as an interlayer insulating layer and comprising an insulating material, after a portion of the second pattern layer is cut by etching and the surface of the first pattern layer is exposed to form the alignment mark, a layer protecting at least the alignment mark is provided, and the circuit forming region of the second pattern layer is then patterned. Therefore, drawbacks resulting from the first pattern layer being exposed, such as the residual etching gas and the first pattern layer reacting with each other after etch-backing when a circuit is formed on the second pattern layer thereby producing a by-product, can be avoided.
The protective layer can be formed, for example, by coating the entire surface with the insulating material, to a thickness at which the second alignment mark is not entirely filled in. Alternatively, resist can be used as a temporary protective layer when a predetermined pattern is formed in the pattern forming region of the second pattern layer by forming resist to a thickness at which the second alignment mark is filled in; forming the predetermined pattern at the pattern forming region of the second pattern layer; and removing the resist to expose the second alignment mark.
When the second alignment mark is formed by cutting the second pattern layer, the second pattern layer can be left and used as a protective layer. Therefore, it becomes unnecessary to use another material to form the protective layer. In this case, the protective layer can be formed merely by changing a way in which the second pattern layer is cut, which is preferable because costs can be reduced and there is no need for additional manufacturing steps.
A second aspect of the present invention is a method of manufacturing an alignment mark for aligning a pattern of a first pattern layer and a pattern of a second pattern layer in a predetermined layout when the first pattern layer and the second pattern layer are layered together, comprising: forming a first alignment mark in a predetermined region of the first pattern layer during the formation of the first pattern layer, and by using the first alignment mark, forming a second alignment mark at a predetermined position of the second pattern layer and forming a predetermined pattern in a pattern forming region of the second pattern layer, wherein a feature size Wm of the second alignment mark and a feature size Wv of a predetermined pattern which is formed on the second pattern layer are determined to satisfy Wv less than Wm less than 2xc3x97Wv.
The diameter Wm of the alignment mark is larger than the diameter Wv of the predetermined pattern formed on the circuit forming region and smaller than twice the diameter Wv of the predetermined pattern formed on the circuit forming region. Therefore, the filling material is filled in the predetermined pattern having the diameter of Wv. At least a thickness Wv of the filling material remains within the alignment mark after the filling material has been coated on the entire surface of a wafer and then removed from the top surface by etch-backing. The remaining filling material acts as the protective layer for the alignment mark.
As a result, drawbacks resulting from the first pattern layer being exposed, such as the residual etching gas and the first pattern layer reacting with each other after etch-backing when the circuit is formed on the second pattern layer, thereby producing a by-product, can be avoided.